Cypress Semiconductor SL811HS Specifiche Scaricare il pdf (Pagina 27)

SL811HS

Document #: 38-08008 Rev. *A Page 27 of 29

7.6.4 Clock Timing Specifications

Parameter Description Min. Typ. Max.

t

CLK

Clock Period (48 MHz) 20.0 ns 20.8 ns

t

HIGH

Clock HIGH Time 9 ns 11 ns

t

LOW

Clock LOW Time 9 ns 11 ns

t

RISE

Clock rise Time 5.0 ns

t

FALL

Clock fall Time 5.0 ns

Clock Duty Cycle 45% 55%

CLK

CLOCK TIMING

trisetfallthigh

tclk

tlow

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