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Chapter 15. Registers Page 15-45

Bit 0 FF Full Flag

FX2 sets FF to 1 to indicate a “full flag” interrupt request. The interrupt source is available in

the interrupt vector register IVEC4.

Do not clear an IRQ Bit by reading an IRQ Register, ORing its contents with a bit mask, and writing

back the IRQ Register. This will clear ALL pending interrupts. Instead, simply write the bit mask

value (with a “1” in the bit position of the IRQ you want to clear) directly to the IRQ Register.

15.7.2 IN-BULK-NAK Interrupt Enable/Request

Figure 15-39. IN-BULK-NAK Interrupt Enable

Figure 15-40. IN-BULK-NAK Interrupt Request

Bit 5-0 EP[8,6,4,2,1,0] Endpoint-Specific Interrupt Enable

These interrupts occur when the host sends an IN token to a Bulk-IN endpoint which has not

been loaded with data and armed for USB transfer. In this case the FX2 SIE automatically

NAKs the IN token and sets the IBNIRQ bit for the endpoint.

Set IE=1 to enable the interrupt, and IE=0 to disable it.

An IRQ bit is set to 1 to indicate an interrupt request. The interrupt source is available in the

interrupt vector register IVEC2. The firmware clears an IRQ bit by writing a 1 to it.

IBNIE IN-BULK-NAK Interrupt Enable (INT2) E658

b7 b6 b5 b4 b3 b2 b1 b0

0 0 EP8 EP6 EP4 EP2 EP1 EP0

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

IBNIRQ IN-BULK-NAK Interrupt Request (INT2) E659

b7 b6 b5 b4 b3 b2 b1 b0

0 0 EP8 EP6 EP4 EP2 EP1 EP0

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

1 2 ... 360 361 362 363 364 365 366 367 368 369 370 ... 459 460

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