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PRELIMINARY

18-Mbit (512K x 36/1Mbit x 18)

Pipelined Register-Register Late Write

CY7C1330AV25

CY7C1332AV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document No: 001-07844 Rev. *A Revised September 20, 2006

Features

• Fast clock speed: 250, 200 MHz

• Fast access time: 2.0, 2.25 ns

• Synchronous Pipelined Operation with Self-timed Late

Write

• Internally synchronized registered outputs eliminate

the need to control OE

• 2.5V core supply voltage

• 1.4–1.9V V

DDQ

supply with V

REF

of 0.68–0.95V

— Wide range HSTL I/O Levels

• Single Differential HSTL clock Input K and K

•Single WE (READ/WRITE) control pin

• Individual byte write (BWS

[a:d]

) control (may be tied

LOW)

• Common I/O

• Asynchronous Output Enable Input

• Programmable Impedance Output Drivers

• JTAG boundary scan for BGA packaging version

• Available in a 119-ball BGA package (CY7C1330AV25

and CY7C1332AV25)

Configuration

CY7C1330AV25 – 512K x 36

CY7C1332AV25 – 1M x 18

Functional Description

The CY7C1330AV25 and CY7C1332AV25 are high perfor-

mance, Synchronous Pipelined SRAMs designed with late

write operation. These SRAMs can achieve speeds up to 250

MHz. Each memory cell consists of six transistors.

Late write feature avoids an idle cycle required during the

turnaround of the bus from a read to a write.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (K). The synchronous

inputs include all addresses (A), all data inputs (DQ

[a:d]

), Chip

Enable (CE

), Byte Write Selects (BWS

[a:d]

), and read-write

control (WE

). Read or Write Operations can be initiated with

the chip enable pin (CE

). This signal allows the user to

select/deselect the device when desired.

Power down feature is accomplished by pulling the

Synchronous signal ZZ HIGH.

Output Enable (OE

) is an asynchronous input signal. OE can

be used to disable the outputs at any given time.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

K,K

BWS

512Kx36

Logic Block Diagram

Data-In REG.

CONTROL

and WRITE

LOGIC

1Mx18

OUTOUT

REGISTERS

and LOGIC

512Kx36

1Mx18

BWS

X = 18:0

X = 19:0

X = a, b

X = a, b, c, d

X = a, b

X = a, b, c, d

Clock

Buffer

MEMORY

ARRAY

(2stage)

[+] Feedback

1 2 3 4 5 6 ... 18 19

Sommario

Pagina 1 - CY7C1332AV25

PRELIMINARY18-Mbit (512K x 36/1Mbit x 18)Pipelined Register-Register Late WriteCY7C1330AV25CY7C1332AV25Cypress Semiconductor Corporation • 198 Champio

Pagina 2 - CY7C1332AV25 (1M x 18)

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 10 of 19tCHCapture Hold after Clock Rise 5 nsOutput TimestTDOVTCK Clock LOW to

Pagina 3

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 11 of 19 Scan Register Sizes Register Name Bit Size—CY7C1330AV25 Bit Size—CY7C1

Pagina 4

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 12 of 19Boundary Scan Order (512K x 36)Bit # Bump ID Bit # Bump ID Bit # Bump I

Pagina 5

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 13 of 19Maximum Ratings(Above which the useful life may be impaired. For user g

Pagina 6

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 14 of 19AC Test Loads and WaveformsNotes: 17. Tested initially and after any de

Pagina 7

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 15 of 19Switching Characteristics[18, 19, 20, 21]Parameter Description250 200Un

Pagina 8

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 16 of 19 Switching WaveformsREAD/WRITE/DESELECT Sequence (OE Controlled)[23, 24

Pagina 9

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 17 of 19READ/WRITE/DESELECT Sequence (CE Controlled)Switching Waveforms (contin

Pagina 10

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 18 of 19© Cypress Semiconductor Corporation, 2006. The information contained he

Pagina 11

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 19 of 19Document History PageDocument Title: CY7C1330AV25/CY7C1332AV25 18-Mbit

Pagina 12

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 2 of 19Selection GuideCY7C1330AV25-250CY7C1332AV25-250CY7C1330AV25-200CY7C1332A

Pagina 13

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 3 of 19Pin DefinitionsName I/O Type DescriptionA Input-SynchronousAddress Input

Pagina 14

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 4 of 19IntroductionFunctional OverviewThe CY7C1330AV25 and CY7C1332AV25 are sy

Pagina 15

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 5 of 19guaranteed. The device must be deselected prior to enteringthe “sleep” m

Pagina 16

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 6 of 19IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial

Pagina 17

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 7 of 19EXTESTEXTEST is a mandatory 1149.1 instruction which is to beexecuted wh

Pagina 18

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 8 of 19 Note: 6. The 0/1 next to each state represents the value at TMS at the

Pagina 19

PRELIMINARYCY7C1330AV25CY7C1332AV25Document No: 001-07844 Rev. *A Page 9 of 19 TAP Controller Block DiagramTAP Electrical Characteristics Over the Op

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