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18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05544 Rev. *F Revised Feburary 07, 2007

Features

• Supports 133 MHz bus operations

• 512K × 36 and 1M × 18 common IO

• 3.3V core power supply (V

)

• 2.5V or 3.3V IO supply (V

DDQ

)

• Fast clock-to-output time

— 6.5 ns (133 MHz version)

• Provides high performance 2-1-1-1 access rate

• User selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• CY7C1381D/CY7C1383D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1381F/CY7C1383F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

Functional Description

[1]

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a

3.3V, 512K x 36 and 1M x 18 synchronous flow through

SRAMs, designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133 MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive edge triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

address pipelining chip enable (CE

), depth-expansion chip

enables (CE

and CE

[2]

), burst control inputs (ADSC, ADSP,

and ADV), write enables (BW

, and BWE), and global write

(GW

). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

allows interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the processor address strobe

(ADSP

) or the cache controller address strobe (ADSC) inputs.

Address advancement is controlled by the address

advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

operates from a +3.3V core power supply while all outputs

operate with a +2.5V or +3.3V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 210 175 mA

Maximum CMOS Standby Current 70 70 mA

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

[+] Feedback

1 2 3 4 5 6 ... 28 29

Sommario

Pagina 1 - CY7C1383D, CY7C1383F

18-Mbit (512K x 36/1M x 18) Flow-Through SRAMCY7C1381D, CY7C1381FCY7C1383D, CY7C1383FCypress Semiconductor Corporation • 198 Champion Court • San Jos

Pagina 2 - (1M x 18)

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 10 of 29Truth Table for Read/Write [4, 9]Function (CY7C1381D/CY7C1381F) GW B

Pagina 3 - Pin Configurations

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1381D/CY7C1383D/CY7C1

Pagina 4 - CY7C1381F (512K x 36)

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 12 of 29Bypass RegisterTo save time when serially shifting data through regi

Pagina 5 - CY7C1383D (1M x 18)

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 13 of 29(Q-bus) pins, when the EXTEST is entered as the currentinstruction.

Pagina 6

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 14 of 293.3V TAP AC Test ConditionsInput pulse levels ...

Pagina 7

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 15 of 29Identification Register DefinitionsInstruction FieldCY7C1381D/CY7C13

Pagina 8

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 16 of 29 119-Ball BGA Boundary Scan Order[14, 15] Bit # Ball ID Bit # Ball I

Pagina 9

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 17 of 29165-Ball BGA Boundary Scan Order[14, 16] Bit # Ball ID Bit # Ball ID

Pagina 10

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 18 of 29Maximum RatingsExceeding the maximum ratings may impair the useful l

Pagina 11 - TAP Controller Block Diagram

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 19 of 29Capacitance [19]Parameter Description Test Conditions100 TQFP Packag

Pagina 12

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 2 of 29Logic Block Diagram – CY7C1381D/CY7C1381F [3] (512K x 36)Logic Block

Pagina 13

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 20 of 29Switching Characteristics Over the Operating Range[20, 21]Parameter

Pagina 14

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 21 of 29Timing Diagrams Read Cycle Timing [26]tCYCtCLCLKtADHtADSADDRESStCHtA

Pagina 15

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 22 of 29Write Cycle Timing [26, 27]Timing Diagrams (continued)tCYCtCLCLKtAD

Pagina 16

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 23 of 29Read/Write Cycle Timing [26, 28, 29]Timing Diagrams (continued)tCYC

Pagina 17

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 24 of 29ZZ Mode Timing [30, 31]Timing Diagrams (continued)tZZISUPPLYCLKZZtZ

Pagina 18

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 25 of 29Ordering InformationNot all of the speed, package and temperature ra

Pagina 19

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 26 of 29Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x

Pagina 20

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 27 of 29Figure 2. 119-ball BGA (14 x 22 x 2.4 mm) (51-85115)Package Diagrams

Pagina 21

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 28 of 29© Cypress Semiconductor Corporation, 2006-2007. The information cont

Pagina 22

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 29 of 29Document History PageDocument Title: CY7C1381D/CY7C1383D/CY7C1381F/C

Pagina 23

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 3 of 29Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBD

Pagina 24

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/1

Pagina 25

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 5 of 29Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable)CY7

Pagina 26

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 6 of 29Pin DefinitionsName IO DescriptionA0, A1, AInput-SynchronousAddress i

Pagina 27

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 7 of 29Functional OverviewAll synchronous inputs pass through input register

Pagina 28

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 8 of 29deasserted and the IOs must be tri-stated prior to the presen-tation

Pagina 29

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 9 of 29Truth Table [4, 5, 6, 7, 8]Cycle DescriptionADDRESS Used CE1CE2CE3ZZ