Document Number: 001-55720 Rev. *H Page 3 of 28
Pinouts
Figure 1. 48-pin SSOP pinout
NC
A
8
Xout
Xin
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
10
V
RTCbat
WE
DQ7
HSB
INT
V
SS
V
CC
V
CAP
V
RTCcap
45
46
47
48
NC
NC
NC
NC
48 - SSOP
(x8)
(not to scale)
Top View
[1]
[1]
Pin Definitions
Pin Name I/O Type Description
A
0
–A
14
Input Address inputs. Used to select One of the 32,768 bytes of the nvSRAM.
DQ
0
–DQ
7
Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.
NC No connect No connect. This pin is not connected to the die.
WE
Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE
HIGH causes the I/O pins to tristate.
X
out
[2]
Output Crystal connection. Drives crystal on start up.
X
in
[2]
Input Crystal connection. For 32.768 kHz crystal.
V
RTCcap
[2]
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if V
RTCbat
is used.
V
RTCbat
[2]
Power supply Battery supplied backup RTC supply voltage. Left unconnected if V
RTCcap
is used.
INT
[2]
Output Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
V
SS
Ground Ground for the device. Must be connected to the ground of the system.
V
CC
Power supply Power supply inputs to the Device. 3.0 V +20%, –10%
HSB
Input/Output Hardware STORE Busy (HSB)
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation, HSB
is driven HIGH for a short time (t
HHHD
) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
V
CAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Left unconnected if RTC feature is not used.
(24 pagine)
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