Cypress Semiconductor CYV15G0404DXB Guida Utente Scaricare il pdf (Pagina 25)

CYV15G0404DXB Evaluation Board

Users Guide

Page 25 of 56

the “MORE” button to customize your clock's settings. Your clock definition needs to be changed to the RXCLKA clock to

trigger on the faster clock.

7. Adjust the power supply to 3.3V and 3 Amps limit.

8. Apply power to the board and the device.

9. Verify that the power supply LEDs (D6 and DT6) are on.

10.Set SPDSELA = HIGH and SPDSELB = MID. Set ULCx = HIGH, LPENx = HIGH for internal loopback, and RCLKENx = LOW.

11.Start transmitting data from the data generator, making sure it is in REPEAT mode.

12.Make sure the jumpers for WREN

(J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page

17).

13.Press and release RESET

to reset the board.

14.Configure the control latches as listed in Table 7-3 for addresses 0 (0000b) through 5 (0101b) for channels A and B.

The following steps are done for result verification on channels A and B:

1. Run the logic analyzer. After it has acquired the data, it will pause and display the data received.

2. Compare the data on channel A with the transmitted data.The data should be the same as the transmitted data except for the

period when TXCT0 is 1. During that period, the 00h input will produce a 05h output, which is the K28.5 framing sequence.

RXSTA[2:0] should be 0 (000b) during data transmission. When the K28.5 framing sequence is being transmitted, RXSTA[2:0]

should be 3 (011b)

3. Repeat the procedure for channel B. However, because REFCLKB is half the frequency rate, only every other data value will

be clocked in. Therefore, the data output from the receiver will be either 05, 01, 04,10, 40,... or 05,00,02,08,20, 80,.... (see

Figure 7-8 on page 24).

7.2.2.2 Encoder Bypass Mode

For channels C and D, complete the following steps:

1. Load the Cypress supplied file 0404BYP.PDA in DG2020 data generator. If you are using your own data generator, use a

waveform similar to the one shown in Figure 7-9.

Table 7-3. Device Control Latch Configuration for Parallel Data Test Mode

ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Reset

Value

(0000b)

ASRFMODE

A[1] = ‘1’

RFMODE

A[0] =’0

FRAMCHAR

A = ‘1’

DECMODE

A = ‘1’

DECBYP

A = ‘1’

RXCKSEL

A = ‘1’

RXRATE

A = ‘0’

GLEN0

= ‘1’

10111111

(0001b)

SDASEL2

A[1] = ‘1’

SDASEL2

A[0] = ‘0’

SDASEL1

A[1] = ‘1’

SDASEL1

A[0] = ‘0’

ENCBYP

A = ‘1’

TXCKSEL

A = ‘1’

TXRATE

A =’0’

GLEN1

= ‘1’

10101101

(0010b)

RFEN

A = ‘1’

RXPLLPD

A = ‘1’

RXBIST

A = ‘1’

TXBIST

A = ‘1’

OE2

A = ‘1’

OE1

A = ‘1’

PABRST

A = ‘0’

GLEN2

= ‘1’

10110011

(0011b)

RFMODE

B[1] = ‘1’

RFMODE

B[0] =’0

FRAMCHAR

B = ‘1’

DECMODE

B = ‘1’

DECBYP

B = ‘1’

RXCKSEL

B = ‘1’

RXRATE

B = ‘0’

GLEN3

= ‘1’

10111111

(0100b)

SDASEL2

B[1] = ‘1’

SDASEL2

B[0] = ‘0’

SDASEL1

B[1] = ‘1’

SDASEL1

B[0] = ‘0’

ENCBYP

B = ‘1’

TXCKSEL

B = ‘1’

TXRATE

B =’0’

GLEN4

= ‘1’

10101101

(0101b)

RFEN

B = ‘1’

RXPLLPD

B = ‘1’

RXBIST

B = ‘1’

TXBIST

B = ‘1’

OE2

B = ‘1’

OE1

B = ‘1’

PABRST

B = ‘0’

GLEN5

= ‘1’

10110011

[9:0]

17C

001

000

3EF

002

004

200

008

000

010

3FF

020

3F7

040

2FF

080

37F

100

3FE

3DF

3FD

3FB

3BF

1FF

3FF

TXDATA

REFCLK

(100 MHz.)

Figure 7-9. Generated Clock and Data Signals for Encoder Bypass Mode from DG2020

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