Cypress Semiconductor enCoRe CY7C601xx Guida Utente Scaricare il pdf (Pagina 30)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 30 of 62

Figure 9. Wakeup Timing

INT

SLEEP

PD

BANDGAP

CLK32K

SAMPLE

SAMPLE

LVD/POR

CPUCLK/

24MHz

BRA

BRQ

ENABLE

CPU

(Not to Scale)

Sleep Timer or GPIO

interrupt occurs

Interrupt is double sampled

by 32K clock and PD is

negated to system

CPU is restarted

after 90ms (nominal)

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