Cypress Semiconductor enCoRe CY7C601xx Guida Utente Scaricare il pdf (Pagina 42)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 42 of 62

Table 65.SPI Mode Timing vs. LSB First, CPOL and CPHA

LSB

First CPHA CPOL Diagram

001

010

011

100

101

110

111

SCLK

SSEL

DATA

X XMSB Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 LSB

SCLK

SSEL

X X

DATA

MSB Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 LSB

SCLK

SSEL

X X

DATA

MSB Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 LSB

SCLK

SSEL

DATA

X XMSB Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 LSB

SCLK

SSEL

DATA

X XMSBBit 2 Bit 3 Bit 4 B it 5 B it 6 Bit 7LSB

SCLK

SSEL

X X

DATA

MSBBit 2 Bit 3 Bit 4 Bit 5 Bit 6 B it 7LSB

SCLK

SSEL

X X

DATA

MSBBit 2Bit 3Bit 4Bit 5Bit 6Bit 7LSB

SCLK

SSEL

DATA

X MSB XBit 2 B it 3 Bit 4 Bit 5 B it 6 B it 7LSB

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 61 62

Microcontrolle 1
CY7C601xx 10
CY7C602xx 10

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