Cypress Semiconductor CY7C1380C Manuale Utente Scaricare il pdf

PRELIMINARY

512K x 36/1M x 18 Pipelined SRAM

CY7C1380C

CY7C1382C

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-05237 Rev. *B Revised December 18, 2002

Features

• Fast clock speed: 250, 225, 200, 167, 133 MHz

• Provide high-performance 3-1-1-1 access rate

•Fast OE

access times: 2.6, 2.8, 3.0, 3.4, 4.2 ns

• Optimal for depth expansion

• 3.3V (–5% / +10%) power supply

• Separate V

DDQ

for 3.3V or 2.5V I/O

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down available using ZZ mode or CE

deselect

• High-density, high-speed packages

• Available in 119-ball bump BGA, 165-ball FBGA and

100-pin TQFP packages

• JTAG boundary scan for BGA packaging version

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1380C and CY7C1382C SRAMs integrate 524,288

× 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

), burst control

inputs (ADSC

, ADSP, and ADV), write enables (BWa, BWb,

c, BWd and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). DQ

a,b,c,d

and DP

a,b,c,d

apply to

CY7C1380C and DQ

a,b

and DP

a,b

apply to CY7C1382C a, b,

c, d each are eight bits wide in the case of DQ and one bit wide

in the case of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP

) or Address Status

Controller (ADSC

) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. Write cycles can be one to

four bytes wide, as controlled by the write control inputs.

Individual byte writes allow individual bytes to be written. BW

controls DQa and DPa. BW

b controls DQ

and DP

. BWc

controls DQc and DPd. BW

d controls DQd-DQd and DPd.

a, BWb, BWc, and BWd can be active only with BWE being

LOW. GW

being LOW causes all bytes to be written. Write

pass-through capability allows written data available at the

output for the next Read cycle. This device also incorporates

pipelined enable circuit for easy depth expansion without

penalizing system performance.

All inputs and outputs of the CY7C1380C and the CY7C1382C

are JEDEC standard JESD8-5-compatible.

Selection Guide

250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.0 3.4 4.2 ns

Maximum Operating Current 350 325 300 275 245 mA

Maximum CMOS Standby Current 70 70 70 70 70 mA

Shaded areas contain advance information.

1 2 3 4 5 6 ... 27 28

Sommario

Pagina 1 - CY7C1382C

PRELIMINARY512K x 36/1M x 18 Pipelined SRAMCY7C1380CCY7C1382CCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-94

Pagina 2

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 10 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1380C/CY7C1382C incorporates a s

Pagina 3

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 11 of 28SRAM and cannot preload the Input or Output buffers. TheSRAM does not implement

Pagina 4

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 12 of 28 TAP Controller State Diagram[7]Note:7. The 0/1 next to each state represent

Pagina 5

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 13 of 28TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating R

Pagina 6

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 14 of 28Set-up TimestTMSSTMS Set-up to TCK Clock Rise 10 nstTDISTDI Set-up to TCK Clock

Pagina 7

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 15 of 28 Identification Register DefinitionsInstruction Field 512K x 36 1M x 18 Descr

Pagina 8

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 16 of 2829 TBD TBD 64 TBD TBD30 TBD TBD 65 TBD TBD31 TBD TBD 66 TBD TBD32 TBD TBD 67 TB

Pagina 9

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 17 of 28Maximum Ratings(Above which the useful life may be impaired. For user guide-lin

Pagina 10

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 18 of 28 Capacitance[13]Parameter Description Test ConditionsMax.Unit100-TQFP 119-BG

Pagina 11

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 19 of 28 tCHZClock to High-Z[16]2.6 2.8 3.0 3.4 3.4 nstCLZClock to Low-Z[16]1.0 1.0 1.3

Pagina 12

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 2 of 28Logic Block Diagram CY7C1380C – 512K × 36Logic Block Diagram CY7C1382C – 1M × 18

Pagina 13

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 20 of 28Read Cycle Timing[4, 18, 20, 21]Note:21. RDx stands for Read Data from Address

Pagina 14

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 21 of 28Read/Write Cycle Timing[4, 18, 19, 20, 21]Switching Waveforms (continued)ADSPC

Pagina 15

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 22 of 28Pipelined Read/Write Timing[4, 18, 19, 20, 21]Switching Waveforms (continued)A

Pagina 16

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 23 of 28Notes:22. Device must be deselected when entering ZZ mode. See Cycle Descriptio

Pagina 17

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 24 of 28Ordering InformationSpeed(MHz) Ordering CodePackageName Package TypeOperatingRa

Pagina 18

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 25 of 28Package Diagrams100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A10151-85

Pagina 19

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 26 of 28Package Diagrams (continued)51-85115-*B119-lead PBGA (14 x 22 x 2.4 mm) BG119

Pagina 20

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 27 of 28© Cypress Semiconductor Corporation, 2002. The information contained herein is

Pagina 21

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 28 of 28Document History PageDocument Title: CY7C1380C/CY7C1382C 512K x 36/1M x 18 Pipe

Pagina 22

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 3 of 28Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAAANCNCVDDQVSSQNCDPaDQaDQaVSSQVDDQDQaD

Pagina 23

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 4 of 28Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNCNCDPcDQcDQdDQcDQdAAA

Pagina 24

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 5 of 28Pin Configurations (continued)CY7C1380C (512K × 36) – 11 × 15 FBGA165-ball Bump

Pagina 25

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 6 of 28Pin DefinitionsName I/O DescriptionA0A1AInput-SynchronousAddress Inputs used to

Pagina 26

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 7 of 28IntroductionFunctional OverviewAll synchronous inputs pass through input registe

Pagina 27

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 8 of 28ignored during this cycle. If a global write is conducted, thedata presented to

Pagina 28

PRELIMINARYCY7C1380CCY7C1382CDocument #: 38-05237 Rev. *B Page 9 of 28Continue Read Next 0 X X 1 X 1 0 0 DQ ReadSuspend Read Current 0 X X X 1 1 1 1 H

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