Cypress Semiconductor Perform CY7C1372D Guida Utente Scaricare il pdf (Pagina 11)

Code for your application layer design can be created in a number of ways: written in VHDL or

Verilog, created in MATLAB, or included as a black box netlist from a third party such as Xilinx or

others. If you design you logic to run on a single clock it is then easier to integrate into the

application layer of the FrameWork Logic. This is usually possible because the other clocks in the

design, such as the A/D sample clocks, or hardware-specific clocks are handled in the hardware

interface layer. The use of a single clock in the application layer allows the designer to use the

timing and physical constraints associated with the hardware interface components.

5.1.1 Using the FrameWork Library in VHDL

The components in the FrameWork Logic library are divided into generic components that may be

used in any design, and hardware-specific components.

The hardware-specific components are used in the designs for A/Ds, DACs, memories and the

like that have unique interface protocols and timings. Constraints in the specific design for IO

standards and specific timing requirements are usually required for use. The constraints for the

hardware-specific components are found in the application example that includes that component.

All hardware-specific components have unique names such as ii_quixote_adc. The naming

convention prevents inadvertent naming collisions with your design if you do not use a ii_ prefix on

your components. The hardware name is included in the name showing which design uses this

component.

In the installation, you will find that hardware-specific components in the directory for that specifc

design. The generic components are in the ii_library directory. To use the compoents, you can

copy them into the design you are creating, or reference the library directory.

Also, you may need to include packages supporting the components in your design. For example,

ii_quixote_dsp_emif_a component requires ii_pkg to be included. This is done by including these

statements in the component and by compiling the package in your design.

library work;

use work.ii_pkg.ALL;

One problem that frequently occurs is that the simulation requires the package be compiled for

use. The script that Xilinx ISE produces seems to exclude these packages for compilation, so be

sure to compile the required packages separately.

Innovative Integration FrameWork Logic User Guide 11

Illustration 2: Logic Architecture Showing Hardware and Application Layers

Interface

Application

Layer

(your logic does here)

Hardware Interface Layer

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Cypress Semiconductor Perform CY7C1372D Guida Utente Pagina 11