Cypress Semiconductor Perform CY7C1372D Guida Utente Pagina 71
- Pagina / 97
- Indice
- SEGNALIBRI
- FrameWork Logic Users Guide 1
- 1 Table of Contents 2
- 2 List of Figures 4
- 3 List of Tables 6
- 4 Introduction 7
- 4.4 Where to Get Help 8
- 5 Logic Development Process 9
- Hardware Interface Layer 10
- Application 11
- (your logic does here) 11
- 5.1.2 VHDL Simulation 12
- 5.2.1 Installation 20
- 5.2.2 MATLAB Simulink Use 22
- SRAM used 24
- 5.4 Loading Logic 27
- 5.4.1 JTAG 27
- 5.4.2.2 Velocia Download 38
- 5.5 Debugging 39
- 5.5.1 Built-in Test Modes 39
- 5.5.2 Xilinx ChipScope 40
- CAUTION: 41
- 6 FrameWork Designs 46
- 6.1.4.2 Memory Map 48
- R/W CE Type 49
- 6.1.4.3 Clocks 51
- 6.1.4.3.1 Clock Sources 52
- 6.1.4.3.2 Domains 53
- 6.1.4.4 A/D Interface 53
- 6.1.4.5 DAC Interface 54
- 6.1.4.6 DSP Interface 55
- 6.1.4.6.1 DSP Bus EMIF A 55
- 6.1.4.6.2 DSP Bus EMIF B 59
- 6.1.4.7 Event Log 59
- 6.1.6 Synthesis and Fitting 60
- 6.1.6.2 Constraints 61
- 6.1.6.2.1 Timing Constraints 61
- 6.1.6.3 Logic Utilization 63
- 6.1.7 Place and Route 66
- 6.1.8 Simulation 68
- 6.1.8.3 Simulation notes 70
- 6.1.9.1 Loading over PCI 70
- 6.1.9.2 Loading over JTAG 70
- 6.2 PMC UWB 71
- 6.2.1 Overview 71
- 6.2.2 Target Devices 71
- 6.2.3 Development Tools 71
- 6.2.4 Application Example 71
- 7 Framework Library 72
- 7.1.1.1 ii_quixote_adc 73
- MATLAB Simulink Component: 75
- 7.1.1.2 ii_quixote_dac 76
- Supported Platforms: Quixote 79
- Description: 79
- Port Direction Function 81
- Target Devices: any 84
- MATLAB Simulink Components: 86
- Target Devices : any 90
- Target Device : Any 94
- 8 Generic Components 95
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