Cypress Semiconductor Perform CY7C1372D Guida Utente Scaricare il pdf (Pagina 84)

Port Direction Function

reset In Global reset for the component

d_clk In The system clock for the system interface.

d_ce In System clock enable.

din[31:0] In Input data

ud_out[31:0] Out

Digital IO output bits

ud_din[31:0] In

Digital IO input bits

ud_config_wr In

Digital IO output configuration write

ud_in[31:0] Out

The ud input register. These are the registered

ud_din bits given to the logic.

ud_rd In

Read enable for the digital IO input register. The

input ud_din pins are read on a rising edge of

d_clk when ud_rd is true.

ud_wr In

Write enable for the digital IO output register

ud_config[4:0] In

Digital IO input configuration controls. In

quixote_intf.vhd, these bits are used as byte

output controls. UD digital IO bytes are outputs

when the ud_config bit is true; i.e. If bit 0 is true,

ud bits 7..0 are outputs.

Table 16ii_quixote_dio Component Ports

Target Devices: any

Innovative Integration FrameWork Logic User Guide 84

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Cypress Semiconductor Perform CY7C1372D Guida Utente Pagina 84